1. Field of the Invention
The present invention relates to a level shifter operative to convert an input signal into an output signal on a different voltage level.
2. Description of the Related Art
A level shifter is employed in a driver to convert an input signal defined relative to a first reference voltage into a signal defined relative to a second reference voltage (see U.S. Pat. No. 5,502,412 on page 8, left column and FIG. 2, for example). An example of such the level shifter is shown in FIG. 8. This level shifter 10′ is operative in accordance with control signals G1, G2, which are generated from an input circuit 20′ through application of a certain conversion to an input signal Vin that is defined relative to a first reference voltage GND (0 V). The input circuit 20′ is driven under a supply voltage VDD (of 5 [V] in this case) defined relative to the first reference voltage GND.
The level shifter 10′ includes p-type high breakdown voltage MOS transistors HMp1 and HMp2, resistors R1 and R2, and a buffer 11 as shown in FIG. 8.
The high breakdown voltage MOS transistor HMp1 has a source connected to the supply voltage VDD, and a drain connected to one end of the resistor R1. The other end of the resistor R1 is connected to a second reference voltage COM (of −90 [V] in this case). Accordingly, a high voltage (VDD−COM=95 [V]) is applied across the source-drain of the high breakdown voltage MOS transistor HMp1. The high breakdown voltage MOS transistor HMp1 is configured to receive the control signal G1 from the input circuit 20′ at the gate to be on/off controlled by the control signal G1.
Similarly, the high breakdown voltage MOS transistor HMp2 has a source connected to the supply voltage VDD, and a drain connected to one end of the resistor R2. The other end of the resistor R2 is connected to the second reference voltage COM. Accordingly, a high-voltage (VDD−COM=95 [V]) is applied across the source-drain of the high breakdown voltage MOS transistor HMp2. The high breakdown voltage MOS transistor HMp2 is configured to receive the control signal G2 from the input circuit 20′ at the gate to be on/off controlled by the control signal G2. The control signals G1 and G2 have opposite logic levels, which can therefore control the high breakdown voltage MOS transistors HMp1 and HMp2 to become conductive alternately.
A supply voltage (15 [V])) is applied to the buffer 11 relative to the second reference voltage COM. The buffer 11 appropriately converts voltages on nodes N1 and N2 originated from currents flowing in the conducted high breakdown voltage MOS transistors HMp1 and HMp2 to provide an output signal Vout relative to the second reference voltage COM.
In the above level shifter, the high breakdown voltage MOS transistors HMp1 and HMp2 are required to have a breakdown voltage of tens of [V], which needs an enlarged size and accordingly an increased capacity. In order to elevate the operation speed in such the level shifter, a large driving current is required to flow in the transistors HMp1 and HMp2. The flow of the large driving current, however, invites a problem associated with an increased consumption power. In contrast, in order to reduce the consumption power, the operation speed should be lowered. Thus, the above level shifter has a trade-off between the reduction in consumption power and the high-speed operation, which are hardly achieved at the same time.